1. Field of the Invention
The present invention relates, in general, to semiconductor structures and methods for fabrication of those structures, and more specifically to a lateral bipolar transistor structure with low base resistance compatible with deep sub-micron (0.25 micron or less) CMOS transistor structures and methods for fabrication.
2. Related Art
The integration of CMOS (complementary metal oxide semiconductor) devices and bipolar devices to provide high performance BiCMOS (bipolar-CMOS) integrated circuits is a well-established technology. These integrated circuits (ICs) take advantage of the high current drive, high transconductance and high speed of bipolar transistors and the low DC power dissipation and high packing density of CMOS transistors to make advanced telecommunications and microprocessor applications possible. However, with the recent advances in semiconductor manufacturing technologies that are making it possible for deep sub-micron CMOS device geometry's (gate widths of 0.25 micron or less) to become manufacturable, the integration of a vertical bipolar transistor in such a CMOS process flow is typically difficult and costly. Thus, new solutions to the integration of bipolar and CMOS technologies need be found to take advantage of the scaling of these sub-micron CMOS devices without increasing process complexity beyond practicability.
One such solution is the substitution of lateral bipolar transistors for the commonly used vertical bipolar transistors. A lateral bipolar transistor differs in structure from that of a vertical transistor in a manner that makes such lateral transistors more easily integrated with CMOS processing.
This relatively easy integration into a CMOS process flow is evidenced by FIG. 1, which shows a cross-sectional view of a portion of a BiCMOS integrated circuit having a lateral NPN transistor 4 formed in the manner of the prior art. It will be understood that while an NPN transistor is described, this is for illustrative purposes only, and that transistor 4 can be a PNP transistor. A P-type semiconductor substrate 10 has a bipolar device region 30 defined by isolation regions 22. A P-type buried layer region 14 is seen to be coupled to a P-type base region 18. Extending from base region 18, buried layer region 14 underlies N-type collector and emitter regions 32 and 36, respectively. Collector and emitter contact regions 46 and 44, respectively, are separated by poly structure 40 overlying dielectric layer 24, and spacers 28 adjacent each sidewall of structure 40, thus defining the width of the active base region 16. Base contact region 48 is separated from collector contact region 46 by isolation region 26. Thus one of ordinary skill in the art can see that poly structure 40, dielectric layer 24 and spacers 28 can be formed concurrent with a CMOS gate structure (not shown); and that collector region 32 and emitter region 36 can be formed simultaneously with CMOS source and drain (S/D) structures (not shown).
However, such conventional lateral bipolar transistors typically suffer from poor performance, as compared to their vertical transistor counterparts. In addition, these conventional lateral transistors can consume a disproportionate amount of surface area. Thus, this combination of performance and space, limit the use of such conventional lateral transistors. For example, F.sub.T and F.sub.MAX, for a typical vertical transistor, can each be as high as 30 GigaHertz (GHz), while for lateral transistor 4, F.sub.T and F.sub.MAX are in the range of 5 MegaHertz (MHz) to 50 MHz. The low F.sub.MAX is due, in major part, to high base resistance R.sub.b, approximately 1 to 10 kilo-ohms (k.OMEGA.) for the prior art devices, (the sum of R.sub.1, R.sub.2 and R.sub.3 as depicted in FIG. 1). While F.sub.T is low due to the large base width, as defined by the length of the poly gate structure. With regard to the surface area consumed, as depicted, transistor 20 requires an area in excess of that of a MOS transistor, having additional area for base region 18 and base contact 48, and isolation region 26.
Thus, it would be advantageous to have a lateral bipolar transistor and method which has increased performance. In addition, it would be advantageous if this lateral bipolar transistor has increased packing density over conventional lateral transistors. It would also be advantageous for this lateral transistor and method could be applicable to either bulk semiconductor substrates or silicon on insulator (SOI) type substrates. Finally, it would be advantageous for this lateral bipolar transistor and method to be easily integrated into deep sub-micron CMOS processing without significantly increasing process complexity or manufacturing costs.